Generally, OFDM is a multi-carrier modulation that includes converting data to be transmitted into complex symbols using M-array quadrature amplitude modulation (M-QAM), converting the complex symbol sequence into a plurality of parallel complex symbols through series-to-parallel conversion, rectangular pulseshaping the plurality of parallel complex symbols, and modulating the rectangular pulseshaped symbols with a plurality of sub-carriers. In OFDM, the frequency interval between the sub-carriers typically is set so that the sub-carrier modulated parallel rectangular pulseshaped signals are orthogonal to each other.
When a M-QAM modulated signal is transmitted through a wireless fading channel without using OFDM and the channel delay spread caused by multi-path delay is greater than the symbol period of the modulated signal, inter-symbol interference (ISI) can be caused, and it may be difficult to restore a signal correctly at a receiver. Accordingly, an equalizer can be employed to compensate random delay spread. However, the configuration of the equalizer may be very complex, and the transmission performance may degenerate greatly due to input noise at the receiver.
In contrast, because OFDM permits the symbol period of each parallel square wave signal to be much longer than the channel delay spread, ISI can be reduced. In addition, because the guard interval can be set to a longer length than the delay spread in OFDM, the ISI can be substantially removed and the sub-carriers can be maintained orthogonal to each other, thus reducing interference between channels. Accordingly, as OFDM can be effective in data transmission through a wireless fading channel, it is now employed as the standard transmission method for European TERRESTRIAL digital television and audio broadcast system. In addition, OFDM is frequently used in a data transmission system using wire channels, such as a digital subscriber loop system or a power line communication system, to reduce transmission performance degeneration due to multi-path reflection.
FIG. 1 illustrates a transmitting part of a data transmission system using OFDM. Referring to FIG. 1, the transmitting part 10 of the data transmission system using OFDM includes an encoder 11, a sub-carrier relocating unit 12, an inverse fast Fourier transform (IFFT) unit 13, a guard interval inserter 14, a low pass filter 15 and a digital-to-analog converter 16. The encoder 11 encodes data to be transmitted into encoded symbols corresponding to sub-carriers in the form of M-QAM, phase shift keying (PSK) and differential PSK (DPSK). The encoder 11 may use many methods to perform channel encoding, including convolution encoding, block encoding, turbo encoding, and the like. The sub-carrier relocating unit 12 relocates symbols corresponding to respective sub-carrier channels provided from the encoder 11 to make it suitable for the IFFT unit 13 (for purposes of the present description, symbols corresponding to respective sub-carrier channels may be referred to as “sub-carriers”). The IFFT unit 13 transforms the symbols in a frequency domain based on the sampling theorem. The guard interval inserter 14 inserts a guard interval in each frame output from the IFFT unit 13 to remove ISI. The low pass filter 15 removes a noise component included in the signal output from the guard interval inserter 14. The digital-to-analog converter 16 converts a digital signal output from the low pass filter 15 into an analog signal. The analog signal converted by the digital-to-analog converter 16 is transmitted through a wire or wireless channel.
FIG. 2 illustrates a receiving part of a data transmission system using ODFM. The receiving part 20 can include an analog-to-digital converter 21, a low pass filter 22, a guard interval remover 23, a fast Fourier transform (FFT) unit 24, a sub-carrier relocating unit 25, and a decoder 26. The analog-to-digital converter 21 converts an analog signal received through the wire or wireless channel into a digital signal. The guard interval remover 23 removes the guard interval from the signal provided through a low pass filter 22. The FFT unit 24 transforms the signals output from the guard interval remover 23 in a time domain. The sub-carrier relocating unit 25 relocates the linear arrangement of sub-carriers in the frequency domain output from the FFT unit 24 to make it suitable for the decoder 26. The decoder 26 includes a deinterleaver and a Viterbi decoder.
As shown in FIGS. 1 and 2, the components included in the transmitting part 10 and the receiving part 20 operate complementary to each other. Therefore, the following description will be made with respect to the transmitting part 10, while the description of the receiving part 20 will be omitted.
The configuration and the operation of the sub-carrier relocating unit 12 will be described in reference to FIG. 3. Referring to FIG. 3, the sub-carrier relocating unit 12 relocates the linear arrangement of the sub-carriers provided by the encoder 11 and supplies the relocated sub-carriers to the IFFT unit 13.
In this specification, it is assumed that the dimensions of the IFFT unit 13 and the FFT unit 24 are both X64. However, the sizes of the IFFT unit 13 and the FFT unit 24 may vary, and the components of each change depending upon their respective sizes. In addition, the data transmission system described follows the 802.11a Wireless LAN standard. In the following description, the contents disclosed in IEEE 802.11a Wireless LAN standard will be referred to and recited.
The encoder 111 outputs the sub-carriers x0-x31, corresponding to angular frequencies 0 to π, and the sub-carriers x32-x63, corresponding to angular frequencies π to 2π, sequentially. As is known by those skilled in the art, IFFT 13 should receive the sub-carriers x32-x63, corresponding to angular frequencies π to 2π (that is, angular frequencies −π to 0), and the sub-carriers x0-x31, corresponding to angular frequencies 0 to π, in order. The sub-carrier relocating unit 12 relocates the linear arrangement of the sub-carriers x0-x63 output from the encoder 11 into a new linear arrangement (x32-x63, x0-x31) as described above.
The internal circuit configuration of the sub-carrier relocating unit 12 is illustrated in FIG. 4, and the timing diagram illustrating operation of the sub-carrier relocating unit 12 is shown in FIG. 5. Referring to FIG. 4, the sub-carrier relocating unit 12 includes a controller C1, memories M1 and M2 and a multiplexer U1. The sub-carriers x0-x31, corresponding to angular frequencies 0 to π, and the sub-carriers x32-x63, corresponding to angular frequencies π to 2π (that is, angular frequencies −π to 0), are sequentially provided from an encoder 11 to the sub-carrier relocating unit 12. The controller C1 controls the sub-carriers x0-x31 to be stored in the memory M1 when they are provided from the encoder 11. Subsequently, the controller C1 controls the sub-carriers x32-x63 to be output through the multiplexer U1 when they are provided from the encoder 11. When all the sub-carriers x32-x63 are output, the controller C1 controls the sub-carriers x0-x31 stored in the memory M1 to be read out and output through the multiplexer U1.
If the sub-carriers x0-x31 that belong to the next frame are provided from the encoder 11 while the sub-carriers x0-x31 are being output though the multiplexer U1, the controller C1 controls the sub-carriers x0-x31 to be stored in the memory M2. Subsequently, the controller C1 controls the sub-carriers x32-x63 to be output through the multiplexer U1 when the sub-carriers x32-x63 are provided from the encoder 11. When all the sub-carriers x32-x63 are output, the controller C1 controls the sub-carrier x0-x31 stored in the memory M2 to be read out and output through the multiplexer U1. The sub-carrier relocating unit 12 relocates the linear arrangement of the sub-carriers provided from the encoder 11 to make it suitable for the IFFT unit 13 and outputs the relocated linear arrangement of the sub-carriers as described above.
However, as described above, the conventional sub-carrier relocating unit 12 may require two memories M1 and M2. When the number of the sub-carriers of one frame is N and one sub-carrier is output from the sub-carrier relocating unit 12 at every clock cycle, a delay of N/2 can occur due to the sub-carrier relocating unit 12.
FIG. 6 illustrates operation of a guard interval inserter 14 shown in FIG. 1. Referring to FIG. 6, the guard interval inserter 14 copies the last 16 sub-carriers x48-x63 to the front of the frame and configures a new frame including 80 sub-carriers x48-x63, x0-x63.
FIG. 7 is a block diagram illustrating an internal circuit configuration of a guard interval inserter 14. FIG. 8 is a timing chart illustrating operation of the guard interval inserter 14. Referring to FIG. 7, the guard interval inserter 14 includes a controller C2, memories M3 and M4, and a multiplexer U2. The controller C2 controls the 64 sub-carriers x0-x63 to be stored in the memory device M3. If the index of the sub-carriers output from IFFT unit 13 is 48 or higher, the controller C2 controls the sub-carriers output from IFFT unit 13 to be stored in the memory M3, and, in addition, output to the low pass filter 15. When all the sub-carriers x48-x63 output from the IFFT unit 13 are output through the multiplexer U2, the controller C2 controls the sub-carriers x0-x63 stored in the memory M3 to be read out and output through the multiplexer U2. Therefore, the guard interval inserter 14 outputs sub-carriers x48, x49, . . . , x63, x0, x1, . . . , x63 as the newly configured frame.
If the sub-carriers x0-x63 that belong to the next frame are input from the IFFT unit 13 while the sub-carriers x0-x63 stored in the memory M3 are being output through the multiplexer U2, the controller C2 stores the input sub-carriers x0-x63 in the memory M4. After all the sub-carriers x0-x63 stored in the memory M3 are read out and output through the multiplexer U2, the controller C2 controls the sub-carriers x48-x63 of the next frame input from IFFT unit 13 to be output through the multiplexer U2. If the sub-carrier x63 is output through the multiplexer U2, the controller C2 controls the sub-carriers x0-x63 stored in the memory M4. The controller C2 controls the sub-carriers x48-x63 of the next frame to be output through the multiplexer U2 after all the sub-carriers x0-x63 stored in the memory M3 are read out and output through the multiplexer U2. When the sub-carrier x63 is output through the multiplexer U2, the controller C2 controls the sub-carriers x0-x63 stored in the memory M4 read out and output through the multiplexer U2.
As described above, the conventional guard interval inserter 14 can reduce ISI by inserting a guard interval into the front of one frame using two memories M3 and M4. However, assuming that the number of sub-carriers in one frame and the number of the sub-carriers belonging to a guard interval are N and G, respectively, and one sub-carrier is output from the sub-carrier relocating unit 12 every clock cycle, the conventional guard interval inserter 14 may introduce a delay of N−G clock cycles. The sum of the delay of the sub-carrier relocating unit 12 described above and the delay due to the guard interval inserter 14 may be N/2+(N−G). Therefore, the total delay of the transmitting part 10 and the receiving part 20 may be N/2+(N−G)+N/2=2N−G. Such a delay can deteriorate the transmission efficiency of the entire communication system.